Power (microprocessor)
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| Power (microprocessor) | |
|---|---|
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| Name | Power (microprocessor) |
| Designer | IBM, Motorola, Freescale Semiconductor, Apple Inc., NVIDIA |
| Introduced | 1990s |
| Architecture | Power Architecture, PowerPC |
| Process | CMOS |
Power (microprocessor)
Power in a microprocessor refers to electrical energy consumption, thermal dissipation, and related supply and management within integrated circuits designed by organizations such as Intel, IBM, AMD, ARM Holdings, and NVIDIA. The metric is central to product development at firms like Apple Inc., Qualcomm, Samsung Electronics, Taiwan Semiconductor Manufacturing Company, and GlobalFoundries where power interacts with performance, cost, and reliability. Power considerations influence roadmap decisions at institutions including DARPA, European Commission, National Institute of Standards and Technology, and companies delivering servers for Amazon Web Services, Microsoft Azure, and Google Cloud Platform.
Overview
Microprocessor power is measured and optimized across multiple industries including consumer electronics from Sony, HTC Corporation, and LG Electronics and enterprise systems by Oracle Corporation and Hewlett Packard Enterprise. Designers use models from research groups at Massachusetts Institute of Technology, Stanford University, University of California, Berkeley, and ETH Zurich to predict energy use under workloads like those from SPECint, SPECfp, and benchmarks from LINPACK or Geekbench. Standards bodies such as JEDEC and IEEE define measurement guidance adopted by manufacturers including Intel Corporation and ARM Ltd..
Power Consumption and Measurement
Measurement techniques rely on instrumentation from vendors like Keysight Technologies, Tektronix, and Rohde & Schwarz and on metrics published by consortia such as Green Grid and The Green Electronics Council. Power is quantified using wall‑plug metrics (total system draw) and on‑chip telemetry provided by Intel RAPL, ARM EnergyProbe, and IBM PowerVM tools, with workloads sourced from SPEC Energy, TPC, Phoronix Test Suite, and telecommunication tests from 3GPP. Energy per operation, power density, and thermal design power (TDP) remain primary published figures for products by NVIDIA Corporation, AMD, Apple Inc., and server vendors selling into data centers run by Facebook and Twitter.
Sources of Power Use (Dynamic vs Static)
Dynamic power arises from switching activity in logic elements designed in CMOS technology and is affected by clock rates used in families like PowerPC and ARM Cortex cores; research groups at University of Cambridge and Imperial College London study switching models for high‑performance cores such as those found in Intel Xeon and AMD EPYC. Static (leakage) power originates from transistor leakage paths exacerbated by scaling nodes developed at TSMC and Samsung Foundry (e.g., 7 nm, 5 nm) and mitigated with techniques adopted by GlobalFoundries and SMIC. Both sources are analyzed with tools from Cadence Design Systems, Synopsys, and Mentor Graphics under workloads like virtualization by VMware or containerized services by Docker Inc..
Power Management Techniques
Power management uses techniques such as dynamic voltage and frequency scaling (DVFS) implemented by Intel SpeedStep, AMD Cool'n'Quiet, and ARM Big.Little scheduling; operating systems such as Linux, Windows NT, macOS, and hypervisors by Xen Project and KVM coordinate policies. Hardware features include clock gating, power gating, multi‑threshold CMOS using IP from ARM Holdings and Imagination Technologies, and on‑die regulators used by Apple A-series and Qualcomm Snapdragon SoCs. System‑level approaches leverage energy‑aware compilers from GNU Project and runtime managers developed at University of Illinois Urbana–Champaign and Carnegie Mellon University.
Architecture and Process Technology Impacts
Instruction set architecture choices such as RISC, CISC, Power Architecture, and microarchitectural features like out‑of‑order execution, superscalar pipelines, and branch predictors influence energy per instruction for implementations by IBM POWER, Intel x86, ARM Ltd., and MIPS Technologies. Process innovations from TSMC, Intel Foundry Services, and Samsung including FinFET, gate‑all‑around, and EUV lithography affect leakage and switching capacitance. Packaging advances such as 2.5D interposers and 3D stacking used by NVIDIA, Intel, and AMD change thermal paths and power delivery requiring co‑design with power delivery networks produced by suppliers like Amkor Technology.
Thermal and Reliability Considerations
Thermal design interacts with cooling solutions from Noctua, Corsair, and data center practices by Equinix and Digital Realty. Thermal hotspots influence electromigration, negative bias temperature instability (NBTI), and time‑dependent dielectric breakdown (TDDB), studied at research centers including IMEC, CSEM, and TÜV SÜD. Reliability standards and warranty practices at manufacturers like Dell Technologies and Lenovo depend on thermal envelopes and accelerated testing performed with chambers by Thermotron.
Design Trade-offs and Optimization Strategies
Design teams at Apple Inc., Intel, AMD, ARM, and NVIDIA balance energy efficiency, performance per watt, cost per transistor, and time‑to‑market. Strategies include heterogeneous computing integrating CPUs, GPUs, NPUs, and FPGAs from Xilinx to offload workloads such as machine learning frameworks like TensorFlow and PyTorch. EDA flows from Cadence, Synopsys, and Siemens EDA enable power analysis, gate sizing, and floorplanning; system integrators such as Cisco Systems and Juniper Networks tune firmware and board power rails to meet service‑level agreements used by cloud operators like Google and Microsoft Azure.