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| PCIe 4.0 | |
|---|---|
| Name | PCIe 4.0 |
| Developer | Intel, AMD, NVIDIA, PCI Special Interest Group |
| Introduced | 2017 |
| Predecessor | PCIe 3.0 |
| Successor | PCIe 5.0 |
| Type | Peripheral Component Interconnect |
| Data rate | 16 GT/s per lane |
| Link width | x1, x2, x4, x8, x16 |
PCIe 4.0 PCIe 4.0 is the fourth-generation iteration of the Peripheral Component Interconnect Express family adopted by the PCI Special Interest Group and integrated into hardware platforms designed by Intel, AMD, and NVIDIA. It doubles raw per-lane throughput relative to the prior generation and has been adopted across server, desktop, and embedded systems developed by companies such as Dell, HP Inc., and Lenovo. Major chipset and motherboard platforms from vendors like ASUS, MSI, and Gigabyte incorporated PCIe 4.0 lanes alongside processors from AMD Ryzen, Intel Core, and accelerator products from Intel Xe, NVIDIA Tesla, and AMD Radeon.
PCIe 4.0 builds on the architectural lineage that includes PCI Express 1.0, PCI Express 2.0, and PCI Express 3.0 while aligning with interoperability goals championed by the PCI Special Interest Group. It was formalized during meetings attended by representatives from Intel Corporation, Advanced Micro Devices, NVIDIA Corporation, Marvell Technology Group, Broadcom Inc., and standards bodies that collaborate with organizations such as IEEE and JEDEC. Market introductions occurred in product roadmaps by AMD in conjunction with server platform discussions involving Amazon Web Services, Microsoft Azure, and Google Cloud Platform.
Key specifications include a raw signaling rate of 16 gigatransfers per second (GT/s) per lane and an effective data rate approximating 2 gigabytes per second (GB/s) per lane after overhead, enabling x16 links to approach 32 GB/s bidirectional throughput—a specification referenced in design literature from Intel and AMD. Electrical and mechanical constraints are governed by connector families used by manufacturers such as Samtec and Molex, and thermal and power envelopes interact with thermal solutions from Noctua and Corsair. Compliance testing is performed in labs associated with Keysight Technologies, Tektronix, and semiconductor foundries operated by TSMC and GlobalFoundries.
The link layer, transaction layer, and physical layer model used in PCIe 4.0 continue the layer definitions present since earlier generations, with enhancements to forward error correction, equalization, and link training introduced by engineering teams at Intel and AMD. Signalling improvements include advanced equalization algorithms informed by research at institutions such as Massachusetts Institute of Technology, Stanford University, and University of California, Berkeley. Channel modeling and signal integrity validation often reference test suites from Ansys and measurement techniques published by Bell Labs and Agilent Technologies alumni.
Performance evaluations of PCIe 4.0 appear in reviews and benchmark suites published by outlets like AnandTech, Tom's Hardware, and PC Gamer, and are used by system architects at cloud providers including Amazon Web Services, Microsoft Azure, and Google Cloud Platform to characterize accelerator and storage performance. Benchmarks comparing NVMe SSDs from Samsung Electronics, Western Digital, Intel, and Micron Technology show sustained bandwidth and IOPS improvements when using PCIe 4.0 links, with graphics card throughput examined in reviews of NVIDIA GeForce and AMD Radeon products.
Adoption timelines were influenced by roadmap announcements from AMD (with platforms such as those supporting Ryzen 3000 series) and later integrations by Intel in server and client chipsets coordinated with partners like ASRock and EVGA. Backward compatibility with earlier PCIe slots is a principle advocated by the PCI Special Interest Group and implemented across motherboards sold by ASUS, MSI, and Gigabyte. Enterprise adoption occurred through appliance vendors such as HPE, Dell EMC, and networking vendors like Cisco Systems integrating PCIe 4.0-capable accelerators and storage controllers.
Typical use cases include high-performance NVMe storage from manufacturers like Samsung, Intel, and Western Digital; GPU and accelerator interconnects for products such as NVIDIA Tesla, AMD Instinct, and FPGA cards from Xilinx used in data centers operated by Google Cloud Platform, Amazon Web Services, and Microsoft Azure. Other implementations include high-bandwidth networking adapters from Mellanox Technologies (now part of NVIDIA), specialized instrumentation from Keysight Technologies, and edge computing appliances designed by firms such as Dell and HPE.
Standardization progressed through working groups within the PCI Special Interest Group with contributions from Intel, AMD, NVIDIA, Broadcom Inc., and testing houses such as Futuretronics and UL Laboratories. The specification's evolution paralleled semiconductor scaling advances produced at foundries like TSMC and process node shifts discussed in conferences such as the International Solid-State Circuits Conference and Hot Chips. Adoption milestones were reported in trade press covering Computex Taipei and CES product announcements by motherboard and system manufacturers.
Category:Computer buses