GIC (ARM)

GIC (ARM)
Name	GIC (ARM)
Caption	ARM Generic Interrupt Controller
Developer	ARM Holdings
Released	2000s
Architecture	ARM architecture
Type	Interrupt controller

GIC (ARM) is the ARM Generic Interrupt Controller, a family of interrupt controller specifications and implementations used in ARM architecture-based systems designed by ARM Holdings to manage interrupt distribution across processor core clusters and system components. It defines interfaces for interrupt prioritization, routing, masking, and acknowledgement that are implemented in SoC designs by vendors such as Qualcomm, Samsung Electronics, Broadcom, NXP Semiconductors, and Texas Instruments. The GIC interfaces with system buses, peripherals, and firmware layers like U-Boot and ARM Trusted Firmware while interoperating with operating systems such as Linux kernel, FreeBSD, and hypervisors like KVM (kernel-based virtual machine).

Overview

The GIC specification provides a standardized mechanism to present interrupts from devices like PCI Express, USB, Ethernet (computer networking), and SATA controllers to cores implementing ARM architecture exception levels. It separates interrupt source state, prioritization, and targeting from processor core interrupt handling paths found in implementations from vendors such as Intel Corporation (as contrast), Marvell Technology Group, and MediaTek. GIC designs support both legacy interrupt models and advanced models used by virtualization layers such as Xen (hypervisor), KVM (kernel-based virtual machine), and Microsoft Hyper-V on ARM platforms. Firmware standards including UEFI and projects like Coreboot and Open Firmware may initialize GIC controllers during platform boot.

Architecture and Components

A GIC device typically comprises distributor, redistributor, CPU interface, and ITS components. The distributor module handles global interrupt state suitable for systems with interconnects like AMBA (Advanced Microcontroller Bus Architecture), AXI (Advanced eXtensible Interface), and APb (Advanced Peripheral Bus). Redistributors map interrupts to ARM Cortex-A clusters and work with CPU interfaces to assert IRQ/FIQ signals to exception level handlers at EL1 and EL3. The Interrupt Translation Service (ITS) integrates with MSI and MSI-X capable devices on interconnects such as PCI Express and works alongside system components from Cadence Design Systems or Synopsys. Control registers and priority queues are accessed via memory-mapped I/O used by firmware from ARM Trusted Firmware and bootloaders like Das U-Boot.

Interrupt Types and Handling

GIC supports multiple interrupt types including SPI, PPI, LPI, ELPI, and SGI. Shared Peripheral Interrupts (SPI) originate from external devices such as PCI Express endpoints and Ethernet (computer networking) adapters; Private Peripheral Interrupts (PPI) are local to processor cores such as Cortex-A72 implementations. Software Generated Interrupts (SGI) enable inter-processor signaling used by SMP kernels like Linux kernel and FreeBSD SMP subsystems. Message Signaled Interrupts (MSI) mapping via ITS allow devices following PCI Express or PCI models to inject LPIs and MSIs. The controller provides prioritization, preemption, and masking operations integrated with exception vectors handled by kernels and hypervisors including Xen (hypervisor), KVM (kernel-based virtual machine), and seL4.

GIC Versions and Evolution

GIC has evolved from early distributor-only models to sophisticated versions with virtualization and ITS features. Early generations were used in platforms by Apple Inc. and embedded vendors; newer releases introduced support for virtualization in versions like GICv2, GICv3, and GICv4, aligning with features in ARMv8-A architecture and ARMv9. GICv3 introduced redistributors and 64-bit interfaces compatible with large core counts seen in designs from Ampere (company) and cloud providers like Amazon Web Services. GICv4 extended message-based interrupt delivery and affinity routing to scale for NUMA topologies in server deployments such as those by Google LLC and Microsoft Azure. Research projects at institutions like University of Cambridge and companies such as NVIDIA have driven specific implementation optimizations.

Programming and Configuration

Software configures GIC through memory-mapped registers and system registers exposed by CPU interfaces, using frameworks in Linux kernel device trees and ACPI tables used by Microsoft Windows on ARM. Initialization routines are present in firmware projects such as ARM Trusted Firmware and U-Boot, and kernel drivers in Linux kernel implement device-tree bindings and interrupt domain mappings. Kernel subsystems including IRQ subsystem (Linux kernel) interact with GIC to map device interrupts to handler vectors in drivers for Network drivers, Storage drivers, and GPU stacks. Virtualization layers use virtualization extensions in ARM architecture to configure virtual CPU interfaces and maintain guest-visible interrupt state across context switches for hypervisors like KVM (kernel-based virtual machine) and Xen (hypervisor).

Hardware Implementations and Integration

SoC integrators implement GIC-compatible controllers in silicon for platforms produced by Qualcomm, Samsung Electronics, Apple Inc., NXP Semiconductors, and cloud providers such as Amazon Web Services Nitro systems. Integrations consider coherence with interconnect fabrics like CCI-400 or CCIX and interactions with system management controllers from vendors like Renesas Electronics and STMicroelectronics. FPGA prototyping and verification are often performed using toolchains from Xilinx and Intel (FPGA) formerly Altera (company), while formal verification and simulation use tools from Cadence Design Systems and Synopsys.

Security and Virtualization Features

GIC supports privileged interrupt handling across EL1, EL2, and EL3 exception levels and integrates with secure firmware such as ARM Trusted Firmware and secure world components like Trusted Execution Environment. Features for virtualization include virtual CPU interfaces, virtual interrupt prioritization, and ITS-assisted MSI routing enabling guests under hypervisors such as KVM (kernel-based virtual machine) and Xen (hypervisor) to receive direct device interrupts. Security considerations intersect with TEEs like TrustZone and remote attestation systems used in cloud platforms like Azure and Google Cloud Platform.

Category:ARM architecture