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| Fastbus | |
|---|---|
| Name | Fastbus |
| Type | Computer bus |
| Developer | CERN and collaborators |
| Introduced | 1980s |
| Discontinued | 1990s (mainstream) |
| Predecessor | VMEbus |
| Successor | CAMAC (concurrent), PCI (later influence) |
| Form factor | Eurocard |
| Voltage | +5V logic |
| Bus width | 32-bit (typical) |
Fastbus is a high-performance crate-based data acquisition backplane developed in the 1970s–1980s for large-scale particle physics experiments at laboratories such as CERN, SLAC, and Fermilab. It provided modular, high-throughput, low-latency interconnects for readout electronics used in experiments like ALEPH, OPAL, CMS, ATLAS, DELPHI and in neutrino experiments at Brookhaven. Designed as a successor to contemporaneous systems like CAMAC and VMEbus, it influenced later standards including PCI and FASTPATH-style custom backplanes.
Development began as collaborations among institutes including CERN, DESY, Brookhaven, Fermilab, and SLAC to meet the needs of experiments at facilities such as the LEP and the Tevatron. Early specification work involved committees with participants from RWTH Aachen, University of California, Berkeley, University of Oxford, Imperial College London, and industrial partners like Philips and Raleigh Electronics. Field deployments occurred during upgrades for experiments at SPS and in detector systems for CERN SPS fixed-target programs. The standardization process paralleled initiatives at IEEE working groups and coordination with projects at CERN computing services. By the 1990s, the rise of commercial standards such as PCI and system-on-chip solutions led to decreased mainstream adoption, though legacy installations persisted at sites including TRIUMF and KEK.
The architecture used 6U and 9U Eurocard mechanics compatible with crates common at CERN and other labs, enabling integration with modules developed at institutions like INFN, Max Planck Institute, and Lawrence Berkeley National Laboratory. Bus arbitration, segment switching, and crate-level controllers were engineered with input from groups at University of Wisconsin–Madison, MIT, and Caltech. Backplane topology accommodated parallel data paths, token-passing and handshake protocols inspired by contemporaneous work at Bell Labs and implementations from IBM research teams. The connector and pinout design drew on standards used by companies such as Fischer Connectors and AMP Incorporated, while thermal and mechanical specifications aligned with rack systems at CERN. Control and timing facilities were coordinated with timing systems used at SLAC and DESY accelerator complexes.
Fastbus provided 32-bit data transfers with multi-segment addressing and direct memory access schemes similar to DMA in Intel-based architectures. Typical signaling used TTL levels compatible with logic families from Motorola and Texas Instruments. The bus supported block transfer rates enabling sustained throughput comparable with early SCSI interfaces and comparable to contemporaneous high-performance buses in Cray and Fujitsu systems for specific use cases. Diagnostics and error-detection borrowed CRC and parity approaches used in systems from Hewlett-Packard and Sun Microsystems. Firmware and microcontroller support often relied on processors such as the Motorola 68000 and microcontrollers from Intel. Timing and synchronization interfaced with clock distribution practices at CERN using fanout modules developed by groups including Fermilab instrumentation.
Implementations were developed by collaborations across CERN experiment groups, industrial firms like Selcon, boutique electronics shops at Università di Bologna, University of Manchester, and instrumentation teams at Brookhaven. Variants included commodity-like readout controllers, crate controllers, digitizer modules, and custom front-end electronics for calorimetry and tracking detectors in experiments such as ALEPH, DELPHI, OPAL, and hadron experiments at CERN PS. Regional adaptations were produced for facilities including KEK in Japan and TRIUMF in Canada, and research labs like JINR implemented localized firmware. Commercial derivative products appeared from vendors such as Struck Innovative Systeme, CAEN, and smaller European suppliers, while firmware ecosystems incorporated toolchains from GCC ports and embedded SDKs from Green Hills Software.
The bus excelled in high-channel-count data acquisition tasks required by electromagnetic calorimeters, drift chamber readout, and muon systems used in experiments at LEP and Tevatron. It supported sustained block transfers for event building and contributed to trigger/readout latency targets in experiments led by collaborations like ATLAS and CMS during early design phases. In fixed-target and neutrino experiments at Fermilab and Brookhaven, implementations facilitated front-end digitization and aggregation comparable to bespoke solutions used in NOvA and MINOS pre-instrumentation phases. Benchmark comparisons at test stands involving hardware from HP and Sun Microsystems showed strong deterministic latency properties favored for synchronous acquisition tasks in accelerator environments managed by CERN operations teams.
Interfacing strategies included bridge modules to convert between Fastbus and crate systems like VMEbus, CAMAC, and later to PCI and VME64x backplanes. Gateways and protocol converters were engineered by groups at Oxford University, Imperial College London, and companies such as Xilinx-based FPGA houses, enabling integration with data acquisition frameworks like MIDAS and EPICS used at Jefferson Lab and SLAC. Software drivers and middleware were often developed for operating systems including VxWorks and Linux distributions maintained by Debian and Red Hat teams at research sites. Test equipment interoperability utilized oscilloscopes and logic analyzers from Tektronix and Agilent Technologies.
Although mainstream use declined with the proliferation of PCI and network-based readout solutions developed by projects at CERN and commercial vendors, the bus influenced subsequent designs in crate-based instrumentation and informed standards in experiment readout architectures used by collaborations such as ALICE and LHCb. Educational and museum pieces remain in collections at institutions like CERN and Science Museum where they document the evolution of data acquisition hardware. Techniques developed for arbitration, error handling, and modular front-end design seeded practices in FPGA-based systems from Xilinx and Altera and influenced industrial control deployments at facilities like Oak Ridge National Laboratory and Lawrence Livermore National Laboratory.
Category:Computer buses Category:Data acquisition systems