EUV lithography

EUV lithography
Name	EUV lithography
Caption	Extreme ultraviolet lithography tool schematic
Invented	1990s
Developers	ASML, IBM, Intel, Samsung Electronics
Wavelength	13.5 nm
Application	semiconductor manufacturing, microprocessor fabrication, memory chip production

EUV lithography is a photolithographic technique used to print sub-10-nanometer features for semiconductor devices on silicon wafers. It evolved from research programs and industrial collaborations involving companies and institutions such as ASML, IBM, Intel, Samsung Electronics, TSMC, Imec and national laboratories including Lawrence Berkeley National Laboratory, Sandia National Laboratories and Eindhoven University of Technology. EUV enabled scaling paths outlined by roadmaps like the International Technology Roadmap for Semiconductors and initiatives led by organizations such as SEMATECH and IEEE.

History

EUV lithography traces roots to extreme ultraviolet and soft X-ray research at facilities like Bell Labs, Lawrence Livermore National Laboratory and Fraunhofer Society in the 1980s and 1990s. Collaborative consortia including SEMATECH and industrial partnerships with ASML accelerated development through prototype programs such as the EUV-LLW efforts and projects at IMEC. Government funding from agencies like the U.S. Department of Energy and initiatives connected to the European Commission supported source, optics, and resist research. Key milestones involved demonstration tools from Xerox PARC spinouts, breakthrough mirrors from companies tied to Carl Zeiss AG, and absorber and pellicle work influenced by work at Tokyo Electron and Nikon Corporation. The path to production maturity was shaped by wafer fabs at TSMC, Samsung Electronics, and Intel Corporation adopting pilot production runs and by standards set by trade organizations including SEMI.

Principles and Technology

EUV lithography uses 13.5 nm photons produced by plasma sources developed by companies and laboratories including ASML, Cymer, Gigaphoton, and research teams at Lawrence Berkeley National Laboratory. The optical stack employs multilayer mirrors fabricated by groups associated with Carl Zeiss AG and facilities such as IMEC and Fraunhofer Society to focus and project patterns from reticles manufactured by mask houses tied to Photronics and Toppan Printing Co., Ltd.. The technology relies on reflective optics instead of transmission lenses, necessitating vacuum environments maintained with pumps supplied by firms like Edwards Vacuum and Pfeiffer Vacuum. Patterning workflows integrate computational lithography tools developed by vendors connected to Synopsys, Cadence Design Systems, and Mentor Graphics (Siemens) for techniques such as optical proximity correction and source-mask optimization that were advanced in academic groups at MIT, Stanford University, and University of California, Berkeley.

Equipment and Components

Primary machines are EUV scanners manufactured by ASML with core subsystems from partners such as Cymer for light sources and Carl Zeiss AG for projection optics. Tool platforms are installed in fabs operated by TSMC, Samsung Electronics, Intel, GlobalFoundries, and research fabs at IMEC and Semiconductor Research Corporation. Key components include the plasma light source, condenser optics from mirror specialists linked to Zeiss research, illumination systems supplied by teams connected to Gigaphoton, reticle stages built using precision motion systems from vendors like KLA Corporation and metrology solutions from Applied Materials and ASML-NV. Infrastructure integration involves cleanroom standards influenced by ISO and utility coordination with firms such as Schneider Electric.

Masking and Resists

EUV reticles are reflective masks produced with multilayer Bragg mirrors and absorber patterns processed by mask shops such as Toppan Printing Co., Ltd., DNP, and Photronics. Mask blank fabrication drew on research from IMEC and Fraunhofer, with inspection and repair methods developed in collaboration with KLA Corporation and Hitachi High-Technologies. Pellicle development included contributions from companies like Nippon Steel and academic groups at University of Tokyo. Chemists and material scientists at institutions like ETH Zurich, University of Minnesota, and industrial teams at DuPont and JSR Corporation advanced EUV resist chemistries and metal-oxide formulations to balance resolution, line-edge roughness, and sensitivity requirements identified in studies by NIST and industry labs at IBM Research.

Resolution, Throughput, and Limitations

Resolution scaling benefited from shorter 13.5 nm wavelength enabling feature sizes pursued by roadmap targets in documents from ITRS and SEMI. Achieving high resolution requires addressing stochastic defects, shot noise, and secondary electron effects studied at Lawrence Berkeley National Laboratory and Sandia National Laboratories. Throughput depends on source power (work by Cymer and Gigaphoton), collector optics lifespan researched with partners such as ASML and IMEC, and resist sensitivity advanced in work at IBM and Intel. Limitations include mask defectivity, pellicle transmission, source reliability, and costs highlighted in analyses by consulting firms such as McKinsey & Company and industry analysts at Gartner.

Industry Adoption and Manufacturing Impact

Major foundries and integrated device manufacturers including TSMC, Samsung Electronics, Intel Corporation, GlobalFoundries, and memory producers such as SK Hynix adopted EUV in high-volume manufacturing nodes. Adoption timelines were coordinated with design houses like ARM Holdings, Qualcomm, NVIDIA, and Broadcom to enable system-on-chip products for customers including Apple Inc. and Google LLC. Supply chain coordination involved equipment suppliers ASML, materials suppliers such as DuPont and JSR Corporation, and logistics partners like Kuehne + Nagel. Economic impact studies by OECD, World Bank, and market researchers at IHS Markit examined capital expenditure, fab investments in regions such as Taiwan, South Korea, United States, and Netherlands, and workforce development through training programs at universities like Nanyang Technological University.

Safety, Environmental, and Economic Considerations

Safety protocols for vacuum and high-energy plasma systems are influenced by standards and regulators such as Occupational Safety and Health Administration and European Chemicals Agency, with compliance programs at fabs like Intel and TSMC. Environmental analyses from EPA and lifecycle assessments in studies by European Environment Agency address chemical use, water consumption, and materials sourcing from suppliers including BASF and Air Liquide. Economic considerations include capital intensity reported by investment banks like Goldman Sachs and policy implications discussed in documents by European Commission and U.S. Department of Commerce. Long-term strategic concerns have involved export controls and trade policy dialogues including stakeholders such as U.S. Congress and trade authorities in China and the European Union.

Category:Semiconductor fabrication