DEC SRC

DEC SRC
Name	DEC SRC
Developer	Digital Equipment Corporation Systems Research Center
Family	DEC high-performance systems
Release	1980s–1990s
Type	Research supercomputer
Os	Proprietary research kernels, Ultrix, BSD
Cpu	Custom microprocessors, experimental VLSI arrays
Memory	Large shared memory configurations
Storage	Disk arrays, RAID explorations
Platform	Research and prototype platforms

DEC SRC The DEC SRC was a family of experimental high-performance computing platforms developed by Digital Equipment Corporation Systems Research Center during the 1980s and early 1990s. Designed to explore scalable shared-memory multiprocessing, advanced compiler techniques, and novel interconnects, the project intersected with research at MIT, Stanford University, University of California, Berkeley, and industrial partners such as Intel and Sun Microsystems. The effort informed later commercial systems from DEC and influenced designs at Cray Research, Hewlett-Packard, and academic projects like Sequent Computer Systems and the SPARC research community.

History

Work on the SRC family grew from earlier multiprocessor and microprocessor initiatives within Digital Equipment Corporation and its Western Research Laboratory and VAX engineering groups. Early prototypes built on lessons from the VAX-11 and VAX 9000 programs and engaged with contemporaneous projects such as CMU multiprocessor experiments and the Seymour Cray-era vector efforts. The SRC effort intensified after the founding of Systems Research Center when researchers sought to prototype scalable cache-coherent shared-memory machines to test ideas from the Berkeley RISC project and the Stanford DASH cache-coherence protocol. Funding and collaboration included ties to Defense Advanced Research Projects Agency initiatives and academic grants from agencies such as the National Science Foundation.

Important milestones included the construction of board-level prototypes integrating experimental VLSI chips and custom interconnects, publication of hardware and software results in venues like the ACM and IEEE conferences, and the transfer of key technologies into DEC commercial lines such as the Alpha and later multiprocessor servers. SRC work intersected with compiler and language research linked to XPL, Fortran, and early C compilers optimized for parallelism, and researchers published results alongside projects like RAID reliability studies and NUMA architecture evaluations.

Architecture and Components

SRC designs emphasized scalable shared-memory with cache coherence across dozens to hundreds of processors. The hardware combined custom microprocessor arrays, experimental VLSI chips inspired by RISC principles, and high-bandwidth interconnect fabrics. The topology integrated switched networks reminiscent of later InfiniBand and interconnect technologies used in Cray T3D systems, with an emphasis on low-latency directory-based cache coherence similar to protocols explored at Stanford and CMU.

Key components included processor boards with multiple CPU cores, dedicated memory controllers supporting large symmetric memory regions, and I/O subsystems that experimented with ideas later seen in SCSI and storage area networks. SRC prototypes used memory consistency models that researchers compared to SC (sequential consistency) and relaxed models investigated in the SPARC and Alpha contexts. Custom bus designs and bridge logic interfaced experimental processors to legacy VAX peripherals and networking hardware such as Ethernet and ATM.

Operating System and Software Environment

The SRC platforms ran a mix of experimental operating system kernels and adapted versions of established systems, including ports of Ultrix and research kernels influenced by BSD and Mach. The software environment supported multithreaded runtime systems, parallel libraries derived from PVM and early MPI concepts, and compilers that implemented automatic parallelization and aggressive optimization strategies born from the Stanford SUIF and Bell Labs compiler work.

System software research produced advances in thread scheduling for large-scale SMPs, page migration policies related to NUMA systems, and debugging and performance tools comparable to later commercial offerings from Sun Microsystems and HP. SRC investigators published on transactional memory precursors, coherence-debugging utilities, and file system experiments that paralleled work on NFS and distributed file systems in academic settings.

Applications and Use Cases

SRC machines served as platforms for research workloads in scientific computing, database systems, and symbolic computation. Benchmarks and applications included parallel numerical codes like those used in Los Alamos National Laboratory simulations, large-scale relational and analytical database experiments inspired by Ingres and System R, and compiler-test workloads for languages such as Fortran and Ada.

Other use cases encompassed graphics and visualization pipelines analogous to those developed at NASA and multimedia processing prototypes influenced by Sun Microsystems graphics research. SRC testbeds also hosted experiments in parallelizing artificial intelligence workloads that connected to efforts at MIT Artificial Intelligence Laboratory and industrial AI research groups at Bell Labs.

Legacy and Influence

Although SRC systems never became mainstream commercial products, their architectural and software discoveries significantly influenced later DEC products and the broader high-performance computing community. SRC research fed into the design of the DEC Alpha processors, multiprocessor server line strategies, and the development of cache-coherent NUMA approaches adopted by vendors such as HP and Oracle Corporation (after acquiring Sun Microsystems technology). Publications and prototypes informed standards and practices in parallel programming, contributing to advances later embodied in MPI and transactional memory research.

Alumni from the SRC program went on to influential roles at Intel, Microsoft Research, Google, and academia, carrying forward ideas into cloud computing, multicore CPU design, and cluster architectures that underpin modern Amazon Web Services and Google Cloud Platform infrastructures. The SRC legacy persists in academic curricula at institutions like MIT, Stanford University, and UC Berkeley, and in museum and archival collections documenting the evolution of shared-memory multiprocessor systems.

Category:Digital Equipment Corporation