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CoreSight

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Article Genealogy
Parent: Cortex-M series Hop 5
Expansion Funnel Raw 89 → Dedup 0 → NER 0 → Enqueued 0
1. Extracted89
2. After dedup0 (None)
3. After NER0 ()
4. Enqueued0 ()
CoreSight
CoreSight
Logo-rework as vector-graphic: Smartcom5Idea: Arm, Ltd., 2011 for ARMv8 · CC BY-SA 3.0 · source
NameCoreSight
DeveloperARM Holdings
TypeDebug and trace architecture
Introduced2000s
WebsiteARM developer

CoreSight is an ARM-developed debug and trace architecture for system-on-chip (SoC) implementations that provides standardized components for debugging, tracing, and performance analysis. It integrates with processors such as the ARM Cortex-M, ARM Cortex-A, and ARM Neoverse families, and interoperates with tools from vendors including Cadence Design Systems, Synopsys, and Siemens. CoreSight enables observation of processor execution, buses, and peripherals across complex designs used by companies such as Apple Inc., Samsung Electronics, Qualcomm, NVIDIA, and Microsoft.

Overview

CoreSight defines a set of modular components—trace sources, trace funnels, trace sinks—that form a debug and trace network on modern SoCs. It supports trace of instruction and data streams from cores like ARM Cortex-R and ARM SecurCore, and synchronizes with system elements such as TrustZone and Virtualization extensions. Designed for integration in products by Broadcom, MediaTek, and Intel Corporation licensees, CoreSight aligns with standards exemplified by IEEE 1149.1 and complements platform efforts from JEDEC and MIPI Alliance. It is widely used in mobile, automotive, and embedded applications where companies such as Bosch, Continental AG, and Tesla, Inc. require in-field diagnostics.

Architecture and Components

The CoreSight architecture comprises standardized blocks: trace sources (for example, processor trace units), trace concentrators, trace port interfaces, and debug access ports. Key components include the Embedded Trace Macrocell (ETM) for instruction trace, the Program Flow Trace (PFT) mechanism, the Instrumentation Trace Macrocell (ITM) for software events, and the System Trace Macrocell (STM) for multi-source trace aggregation. On-chip interconnects such as those designed by ARM AMBA facilitate trace transport, while off-chip export options use interfaces like JTAG and Serial Wire Debug. Fabric vendors like Xilinx and Altera (now part of Intel FPGA) implement CoreSight interconnects in their programmable devices.

Debug and Trace Protocols

CoreSight supports protocols for real-time, non-intrusive observation including instruction trace and data trace protocols compatible with processor debug architectures from ARM Ltd. and partners. It works with transport technologies such as ETB (Embedded Trace Buffer) and TPIU (Trace Port Interface Unit) for formatting trace packets, and uses packet protocols aligned with industry trace analyzers from Percepio and Lauterbach. The debug access conforms with standards like IEEE 1149.7 and interacts with debug agents used by firms including Green Hills Software, Wind River Systems, and Red Hat for embedded Linux traces.

Implementation and Integration

SoC integrators embed CoreSight components within chips produced by foundries such as TSMC, GlobalFoundries, and Samsung Foundry. Integration requires coordination with operating systems including Linux kernel, Android (operating system), and real-time operating systems from FreeRTOS and QNX. Hardware description and verification use tools from Synopsys VCS, Cadence Incisive, and Mentor Graphics (now part of Siemens EDA). Major OEMs like Dell Technologies, HP Inc., and Lenovo incorporate CoreSight-enabled SoCs into devices that run software from Canonical and Microsoft Windows ecosystems.

Tools and Software Support

A rich ecosystem supports CoreSight including debuggers and trace tools from Lauterbach GmbH, Arm Development Studio, and open-source projects like OpenOCD. Trace analysis is provided by vendors such as Percepio AB and Kovio and integrated into IDEs from Eclipse Foundation and Visual Studio Code. Continuous integration and testing systems from Jenkins and GitLab pipelines can capture trace data for regressions, while performance suites like SPEC and profiling tools from Google have been adapted to utilize CoreSight traces for benchmarking.

Use Cases and Applications

CoreSight is used for software debugging, performance profiling, system validation, and compliance testing in sectors including automotive ADAS projects from Bosch and Continental AG, mobile platforms by Samsung Electronics and Google (company), networking equipment by Cisco Systems and Juniper Networks, and consumer electronics from Sony Corporation and LG Electronics. It enables developers from ARM ecosystem partners such as STMicroelectronics, NXP Semiconductors, and Renesas Electronics to trace multicore interactions, support post-silicon bring-up by teams at Intel Corporation and AMD, and assist research at institutions like MIT and Stanford University.

Security and Privacy Considerations

Because CoreSight provides deep visibility into execution and data flows, access controls and privilege management are critical. Integration with security frameworks like ARM TrustZone and secure boot mechanisms implemented by Trusted Computing Group members helps mitigate risks. Threat models from organizations such as OWASP and findings from researchers at University of Cambridge, University of California, Berkeley, and ETH Zurich highlight the need for secure debug interfaces, authentication, and audit logging. Vendors including Qualcomm and Apple Inc. implement restrictions on CoreSight access in shipping devices to balance diagnostic capability with protection against physical and firmware attacks.

Category:ARM processors Category:Debugging tools