Avalon (Altera)
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| Avalon (Altera) | |
|---|---|
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| Name | Avalon (Altera) |
| Developer | Altera |
| Introduced | early 2000s |
| Type | On-chip interconnect |
| Application | FPGA, SoC |
| Website | Altera (now Intel FPGA) |
Avalon (Altera) is an on-chip interconnect specification developed by Altera for use in field-programmable gate array (FPGA) systems and system-on-chip (SoC) designs. It defines a family of bus and streaming interfaces, signal conventions, and component roles intended to standardize communication among intellectual property (IP) cores, peripherals, memories, and processors such as Nios II and ARM cores within Altera/Intel FPGA ecosystems. Avalon is widely used in designs involving Quartus Prime, Qsys, Platform Designer, and Stratix, Cyclone, and Arria device series.
Overview
Avalon was created to provide consistent interfaces for IP reuse across Altera toolflows such as Quartus II, Quartus Prime, and Platform Designer (formerly Qsys). It addresses connectivity among IP from vendors including Intel FPGA (Altera), Analog Devices, Xilinx (as a comparative reference), and third-party vendors integrated via tools like ModelSim, VHDL, and Verilog flows. Avalon defines master and slave roles for components such as memory controllers, DMA engines, Ethernet MACs, PCIe endpoints, and processors like Nios II and ARM Cortex-A systems. The specification coexists in ecosystems alongside standards such as AMBA AXI, Wishbone, and TileLink in multicore and heterogeneous designs deployed on Stratix, Cyclone, and Arria families.
Architecture and Components
The Avalon architecture includes multiple interface variants—Avalon Memory-Mapped (MM), Avalon Streaming (ST), Avalon Memory-Mapped Conduit, and Avalon-MM Lite—each suited for different IP types such as SDRAM controllers, HPS subsystems, Ethernet MACs, and custom accelerators. Core components in a Platform Designer system include interconnect fabric modules, arbiters, bridges, master agents (DMA engines, processors), and slave agents (on-chip RAM, flash controllers, UARTs). Typical implementations combine controllers for DDR, QSPI, and HBM with peripheral IP from vendors like Intel FPGA IP Catalog, Micron memory PHYs, Analog Devices transceivers, and Broadcom networking PHYs. Device families such as Stratix 10, Arria 10, Cyclone V, and Agilex influence component choices and timing closure strategies in large FPGA SoC designs.
Avalon Interfaces and Signals
Avalon-MM defines a set of signals for address, data, byte-enable, read, write, waitrequest, and readdata/readdatavalid for synchronous memory-mapped transactions, allowing masters like Nios II and DMA controllers to access slaves such as SDRAM controllers and on-chip RAM. Avalon-ST specifies streaming signals including valid, ready, startofpacket, endofpacket, and fixed-width data paths for IP like Ethernet MACs, PCI Express, and video codecs. Conduit interfaces provide flexible pin-level connections for vendor IP such as ADCs, DACs, and transceiver PHYs. Implementation in HDL uses VHDL or Verilog templates and IP wrappers compatible with simulation tools like ModelSim and QuestaSim, and synthesis flows targeting tools such as Synopsys Synplify in addition to Intel's Quartus.
System Integration and Usage
Platform Designer/ Qsys automates instantiation and interconnection of Avalon components, handling address map generation, clock-crossing bridges, and interrupt routing for processors like Nios II or ARM Cortex-M in heterogeneous systems. Designers integrate IP from Intel FPGA IP Catalog, third-party vendors like Xilinx IP via bridging logic, or open-source cores following Avalon conventions for peripherals including UARTs, SPI controllers, timers, and DMA engines. Integration tasks often involve setting up DDR controllers, configuring PCIe or USB endpoints, and connecting high-throughput channels using Avalon-ST for video processing pipelines used with IP from companies like Intel, Broadcom, and Texas Instruments.
Performance and Implementation Considerations
Avalon’s performance depends on interconnect topology, arbitration schemes, bus width, clock domains, and bridge latencies. For high-bandwidth requirements, designers employ wide data paths, pipelined transactions, and Avalon-ST channels to minimize backpressure overhead with components such as HBM controllers, PCIe Gen3/Gen4 endpoints, and AXI-bridged accelerators. Timing closure and area trade-offs are influenced by device family (Stratix, Arria, Cyclone, Agilex), synthesis settings, and HDL coding style. Cross-domain synchronization often uses clock-crossing FIFOs or CDC bridges when connecting IP running at different clock rates, mirroring patterns used with AMBA AXI interconnects in heterogeneous SoC designs.
History and Development
Avalon originated within Altera in the early 2000s to standardize internal IP connectivity and to simplify integration in Quartus-based designs. Over time, Avalon evolved alongside Platform Designer (Qsys) and Altera’s IP Catalog, with successive device families adding performance features and support for high-speed PHYs. Following Altera’s acquisition by Intel, Avalon remained a core interconnect in Intel FPGA workflows, coexisting with broader industry standards like ARM AMBA and open-source initiatives. Key milestones include the introduction of Avalon-ST for streaming applications, enhanced bridge support for AXI/AXI4, and integration tools enabling faster IP assembly in Platform Designer.
Comparison with Other Bus/Interconnect Standards
Avalon is often compared to ARM AMBA AXI, APB, AHB, Wishbone, and TileLink. Compared with AXI, Avalon-MM is simpler in transaction ordering and signal set, while Avalon-ST parallels AXI-Stream for streaming data but differs in naming and optional flow-control semantics. Wishbone and Avalon share similar goals in open reuse-friendly interconnects, though Wishbone targets open-source cores while Avalon is vendor-centric within Altera/Intel toolchains. Bridge IP commonly connects Avalon to AXI or PCIe fabrics when integrating external IP such as ARM cores, Xilinx accelerators, or third-party peripherals. Designers select Avalon when using Intel FPGA IP, Quartus Platform Designer automation, or when reusing Altera-specific cores like Nios II, while cross-vendor or standards-driven ecosystems may favor AMBA AXI or open interconnects like TileLink.
Category:Altera IP