ARM CoreSight

ARM CoreSight
Logo-rework as vector-graphic: Smartcom5Idea: Arm, Ltd., 2011 for ARMv8 · CC BY-SA 3.0 · source
Name	ARM CoreSight
Developer	ARM Holdings
Introduced	2005
Architecture	ARM
Type	Debug and Trace

ARM CoreSight

ARM CoreSight is a family of debug and trace components developed by ARM Holdings for System on Chip designs. It provides standardized interfaces and protocols to observe, control, and trace processor cores and interconnects during development and field diagnostics. CoreSight integrates with cores, peripherals, and external tools to enable visibility into complex systems used in consumer electronics, automotive, and aerospace products.

Overview

CoreSight provides a modular set of components that enable non-intrusive observation of processor state and system traffic. The technology targets designs based on ARM Cortex series processors such as Cortex-M and Cortex-A, and interfaces with silicon vendors like Qualcomm, Samsung Electronics, Texas Instruments, NVIDIA Corporation, and MediaTek. CoreSight supports industry tools from Arm Ltd. partners including Lauterbach, Segger, ARM Keil, Green Hills Software, and Wind River Systems for software debug, profiling, and trace analysis.

Architecture and Components

CoreSight architecture is built from modular elements including trace sinks, trace funnels, trace ports, and debug access points. Key components include Embedded Trace Macrocell (ETM), Instruction Trace Macrocell (ITM), Program Flow Trace (PFT), Trace Port Interface Unit (TPIU), and Debug Access Port (DAP). ETM integrates tightly with cores such as Cortex-A9 and Cortex-R5, while TPIU exports trace over physical interfaces standardized by organizations like JEDEC and adopted by vendors such as Xilinx and Intel Corporation. The design also incorporates system-level elements such as Cross Trigger Interface (CTI) and System Trace Macrocell (STM) to correlate events across multiple subsystems developed by companies like NXP Semiconductors and STMicroelectronics.

Debug and Trace Protocols

CoreSight implements protocols for instruction trace, data trace, and system event trace. Instruction trace formats align with specifications used by debuggers from GDB-based toolchains and commercial IDEs like Eclipse and Visual Studio Code extensions. Trace transport can use Serial Wire Debug (SWD) and JTAG physical layers standardized by IEEE working groups and supported by probe manufacturers such as SEGGER J-Link and ARM DSTREAM. Trace aggregation and time-stamping rely on synchronization primitives reviewed in standards committees including MIPI Alliance and committees where companies like Sony and Panasonic collaborate.

Implementation and Integration

Silicon vendors implement CoreSight components inside System on Chip platforms alongside interconnects like AMBA and bus fabrics designed by Arteris IP. Integration spans real-time operating systems such as FreeRTOS, Linux kernel, and embedded stacks from Micrium. Toolchains from GCC and LLVM include support for CoreSight-assisted profiling and performance counters. Board-level integration leverages debug connectors and adapters supplied by ecosystem players like Segger, Lauterbach, and ARM Development Studio partners to connect target boards to workstation environments running software from Eclipse Foundation-based IDEs.

Use Cases and Applications

CoreSight is used in scenarios that require visibility into low-level execution for debugging, performance analysis, and compliance testing. In automotive, companies like Bosch and Continental AG use trace for Advanced Driver-Assistance Systems development conforming to ISO 26262. In mobile, vendors such as Samsung Electronics and Qualcomm employ CoreSight for power optimization and system profiling in devices compliant with 3GPP releases. In aerospace and defense, organizations like BAE Systems and Rolls-Royce Holdings use trace for verification and validation in safety-critical avionics platforms governed by standards from RTCA and DO-178C.

Security and Access Control

Access control for CoreSight components is critical in multi-tenant and secure environments. Implementations use trust architectures like ARM TrustZone and secure boot flows coordinated with vendors such as Infineon Technologies and NXP Semiconductors to restrict debug and trace capabilities. Management of debug access integrates with lifecycle control frameworks used by Intel Corporation and AMD to prevent unauthorized extraction of intellectual property. Compliance with export control regimes and certifications by bodies like Common Criteria and Federal Aviation Administration influences how vendors expose CoreSight interfaces on commercial products.

History and Evolution

CoreSight originated as ARM extended debug infrastructure in the early 2000s and evolved through milestones aligned with ARM processor generations. Major revisions coincided with the proliferation of multicore designs and advanced SoC requirements addressed by partners including Broadcom, Marvell Technology Group, and Sony Semiconductor. The ecosystem matured alongside open toolchain advances from projects like GNU Project and standardization efforts influenced by IEEE and JEDEC. Continued evolution tracks requirements from sectors represented by companies such as Apple Inc., Google LLC, and Microsoft for mobile, cloud-edge, and mixed-criticality systems.

Category:ARM architecture