UCIe

UCIe. It is an open industry standard defining a high-bandwidth, low-latency, energy-efficient interconnect for connecting multiple semiconductor dies, or chiplets, within a single package. The specification aims to establish a complete ecosystem for a die-to-die interconnect, covering the physical layer, protocol stack, software model, and compliance testing. Developed by a broad consortium of industry leaders, it is designed to enable an open Chiplet ecosystem, allowing for mixing and matching of chiplets from different suppliers to build advanced SoCs.

Overview

The standard was announced in March 2022 by a founding consortium that included Intel, AMD, Arm, Google, Meta, Microsoft, Qualcomm, Samsung, and TSMC. Its creation was driven by the growing challenges of Moore's law and the increasing cost and complexity of monolithic semiconductor fabrication at advanced process nodes. By promoting a disaggregated, multi-chiplet design approach, it seeks to improve yield, reduce time-to-market, and optimize performance and cost by integrating specialized dies built on different foundry processes. The USB-like naming convention hints at its ambition to become a ubiquitous, foundational standard for heterogeneous integration.

Technical Specifications

The specification defines two primary form factors: the standard package, optimized for high performance and bandwidth density, and the advanced package, which enables even higher performance for demanding applications like HPC and AI. It utilizes a high-speed differential signaling interface, supporting multiple data rates and leveraging well-established electrical interfaces from PCIe and CXL. The physical layer includes specifications for bump pitch, channel reach, and signal integrity, ensuring robust communication between chiplets. Key metrics include target bandwidth densities exceeding those of traditional organic substrates and support for various channel lengths to accommodate different package architectures.

Architecture and Components

The architecture is built on a layered model, comprising the Physical Layer, the Die-to-Die Adapter, and the Protocol Layer. The Physical Layer handles the electrical signaling, clocking, and initial link training. The Die-to-Die Adapter provides critical link management functions, including flit encoding, cyclic redundancy check (CRC), and link state power management. At the Protocol Layer, the standard natively transports two industry-standard protocols: PCIe and CXL. This allows chiplets to communicate using established, software-compatible transaction protocols for I/O and memory semantics, enabling cache-coherent interconnects crucial for data center and accelerator workloads.

Implementation and Ecosystem

Successful implementation relies on a complete ecosystem involving EDA tool vendors, IP providers, foundries, and IDMs. Companies like Synopsys and Cadence Design Systems provide essential design and verification IP. The consortium manages the specification and a compliance program to ensure interoperability between chiplets from different vendors, similar to the role played by the PCI-SIG for PCIe. This open model is intended to foster innovation and competition, allowing a designer to potentially combine a GPU from one vendor, an AI accelerator from another, and HBM from a third within a single package.

Comparison with Alternative Standards

Prior to its introduction, several proprietary and limited-scope die-to-die interconnects existed, such as Intel's AIB and TSMC's LSI LIPINCON. These were often tied to a specific company's packaging technology or foundry process. In contrast, UCIe is an open, royalty-free standard backed by a wide consortium. While other open standards like BoW (Bunch of Wires) from the Open Compute Project also target chiplet connectivity, UCIe differentiates itself with its comprehensive stack supporting mainstream protocols like CXL and its backing by the major commercial semiconductor industry players, giving it significant momentum for broad adoption.

Applications and Use Cases

The primary application is enabling advanced, heterogeneous integration for next-generation computing platforms. Key use cases include disaggregated CPUs and DPUs for cloud servers, complex AI training and inference accelerators that combine compute, memory, and I/O chiplets, and high-performance GPUs. It is also pivotal for creating modular SoCs for client devices, allowing for customization and faster design cycles. The technology supports the vision of "Semiconductor Lego," where system architects can assemble best-in-class components from a global supply chain to meet specific performance, power, and cost targets for markets ranging from automotive to edge devices. Category:Computer buses Category:Computer hardware standards Category:Integrated circuits