RibbonFET

RibbonFET is an advanced semiconductor device architecture for field-effect transistors, representing Intel's implementation of a gate-all-around FET (GAAFET) design. It is a key innovation slated for introduction at the Intel 20A process node, intended to succeed the long-dominant FinFET structure. The architecture features multiple narrow silicon channels, or "ribbons," completely surrounded by the transistor gate, enabling superior electrostatic control. This design is central to continuing Moore's law and advancing performance in future integrated circuits for applications from high-performance computing to mobile devices.

Overview

The RibbonFET represents a fundamental shift in transistor design pioneered by Intel to address scaling limitations encountered with FinFET technology. As defined by the International Roadmap for Devices and Systems, moving to gate-all-around structures is essential for continued miniaturization. The architecture was publicly detailed as part of Intel's process and packaging roadmap update, positioning it as a cornerstone for their post-FinFET era. Its development is a direct response to the challenges outlined by Semiconductor Industry Association research regarding power consumption and performance at advanced nodes.

Device structure and operation

The core of the RibbonFET features multiple parallel, nanometer-scale silicon channels suspended above the substrate. Each ribbon is fully enveloped by a high-κ dielectric material and the gate electrode, forming a gate-all-around configuration. This structure provides enhanced electrostatic control over the charge carrier channel compared to a FinFET, significantly reducing leakage current. The number of stacked ribbons can be adjusted to modulate drive current, offering design flexibility. Operation involves applying a voltage to the gate to create an inversion layer within the silicon ribbons, allowing current to flow between the source and drain.

Fabrication process

Fabricating RibbonFETs requires advanced nanotechnology and lithography techniques, such as extreme ultraviolet lithography. The process begins with epitaxial growth of alternating silicon and silicon germanium layers on a silicon wafer. Using dry etching, fin structures are patterned, which are then selectively etched to remove the silicon germanium layers, leaving behind suspended silicon nanoribbons. A critical step involves the deposition of an interfacial layer and a high-κ dielectric like hafnium oxide, followed by metal gate deposition. This complex flow leverages expertise from research at institutions like IMEC and the University of California, Berkeley.

Advantages and challenges

Key advantages include superior short-channel control, which allows further voltage scaling and reduced dynamic power. The design offers higher drive current per footprint and improved performance at lower supply voltage compared to FinFETs. However, significant challenges remain, including precise control of ribbon thickness and surface roughness, managing parasitic capacitance between stacked ribbons, and the inherent complexity and cost of the manufacturing process. Variability in etch and deposition steps also presents a major yield hurdle for high-volume production.

Applications

RibbonFET technology is primarily targeted at leading-edge microprocessors and system-on-a-chip designs for data centers, artificial intelligence accelerators, and advanced client computing. Its power efficiency benefits are crucial for next-generation mobile processors in smartphones and laptops. The architecture will also enable more powerful and efficient integrated circuits for autonomous vehicles, 5G infrastructure, and edge computing devices. Companies like Qualcomm and Apple Inc. are likely to adopt similar GAA technologies for their future chipsets.

Comparison with other transistor architectures

Compared to the planar transistor, RibbonFET offers vastly better electrostatic integrity. Against the FinFET, it provides superior gate control by surrounding the channel on four sides instead of three, reducing off-state current. Another GAA variant, the nanosheet FET, is functionally similar, with the main distinction often being the aspect ratio of the channel; RibbonFET typically implies a taller, narrower channel. It is considered the evolutionary successor to the FinFET, much as the FinFET succeeded the planar transistor at the 22 nm node. Competing foundries like Samsung Electronics and Taiwan Semiconductor Manufacturing Company are developing analogous architectures under names like Multi-Bridge Channel FET.