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Bonnell (microarchitecture)

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Article Genealogy
Parent: Intel Atom Hop 4
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Bonnell (microarchitecture)
NameBonnell
DesignerIntel
Bits32-bit
Introduced2008
SuccessorSaltwell
PredecessorCore
Variant ofIntel Atom

Bonnell (microarchitecture). Bonnell is a low-power, in-order execution microarchitecture designed by Intel for its first-generation Atom processors, targeting the netbook, nettop, and mobile internet device markets. Introduced in 2008, it represented a significant departure from Intel's performance-oriented Core designs, prioritizing extreme power efficiency and cost-effectiveness. The architecture was foundational for Intel's entry into the ultra-mobile and embedded computing spaces, competing with designs from ARM Holdings and VIA Technologies.

Overview

The Bonnell microarchitecture was unveiled by Intel in March 2008 as the foundation for the Atom processor family, a direct response to the growing market for low-cost, internet-centric devices. Its development was closely tied to the success of the ASUS Eee PC and the emerging netbook category. The design philosophy centered on achieving a very low thermal design power (TDP), often between 0.65 and 2.5 watts, to enable fanless designs and long battery life. This focus positioned Bonnell against competing architectures like the ARM Cortex-A8 in the mobile device arena and older x86 designs from AMD and VIA Technologies.

Design and features

Bonnell employed a simple, in-order execution pipeline, contrasting sharply with the complex out-of-order execution used in contemporary Intel Core 2 processors. This design choice drastically reduced die size, power consumption, and manufacturing cost. Key features included Hyper-Threading Technology, allowing a single physical core to execute two threads simultaneously, improving throughput in multitasking scenarios common in Microsoft Windows environments. The architecture also integrated a system agent and a memory controller on-package in a multi-chip module, rather than on-die, alongside the Poulsbo chipset. It supported the SSE3 instruction set and utilized a 16-stage pipeline.

Processor cores

The microarchitecture was implemented in two primary core variants: Silverthorne and Diamondville. The Silverthorne core, manufactured on a 45 nm process, was designed for Mobile Internet Devices (MIDs) and ultra-mobile PCs, featuring a TDP as low as 0.65W. The Diamondville core, also on 45 nm, was aimed at netbooks and nettops, with slightly higher TDPs. Both cores were single-core designs that leveraged Hyper-Threading. A dual-core variant, codenamed Pineview, later integrated the GPU and memory controller onto the same die as the CPU cores, further reducing platform power and cost. These cores powered processors like the Atom N270, Atom Z5xx series, and Atom D4xx series.

Implementations

Bonnell-based processors were implemented across a wide range of devices and form factors. They were the heart of countless netbook models from manufacturers like Acer, Dell, HP, and Lenovo, typically running Windows XP or Linux distributions. In the embedded systems market, they found use in industrial PCs, point-of-sale terminals, and in-vehicle infotainment systems. Notable implementations include the Intel Atom processor Z5xx series for MIDs, the Atom N2xx series for netbooks, and the Atom D4xx/D5xx series for nettops and embedded applications. The architecture also served in NASA's Spaceborne Computer experiment on the International Space Station.

Successor and evolution

Bonnell was directly succeeded by the Saltwell microarchitecture, which debuted in 2012 as part of the Atom "Centerton" and "Cedarview" platforms. Saltwell maintained the in-order execution design but was manufactured on a more advanced 32 nm process, offering improved performance-per-watt. The architectural lineage continued with the Silvermont microarchitecture, which introduced an out-of-order execution design and a significant leap in performance and efficiency. The technologies and market lessons from Bonnell ultimately influenced Intel's later low-power initiatives, including the Quark microcontroller family and aspects of the Tremont hybrid architecture used in Lakefield processors.

Category:Intel microarchitectures Category:2008 introductions